The W972GG6KB is a 2G bits DDR2 SDRAM, and speed involving -18, -25/25I, and -3/-3I.
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and /CLK)
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
Posted /CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
属性 | 数值 |
---|---|
存储器大小 | 2Gbit |
组织 | 256M x 8 bit |
SDRAM类 | DDR2 |
数据速率 | 800MHz |
数据总线宽度 | 16Bit |
位址总线宽 | 17Bit |
每字组的位元数目 | 8Bit |
最长随机存取时间 | 0.4ns |
字组数目 | 256M |
安装类型 | 贴片 |
封装类型 | WBGA |
引脚数目 | 84 |
尺寸 | 12.6 x 8.1 x 0.6mm |
高度 | 0.6mm |
长度 | 12.6mm |